44:20
lecture1- Introduction to broadband digital communication
Satish Kashyap
31:02
lecture2 - Introduction to broadband digital communication
29:27
lecture3 - Serializers and Deserializers
43:39
lecture4.flv
37:51
lecture5 - CMOS logic, single ended data transmission, limitations
36:18
lecture6 - Current mode logic - Basic circuit design
32:06
lecture7 - Current mode logic - MUX, XOR, Latch
28:20
lecture8 - Current mode logic - Latch design
33:37
lecture9 - Current mode logic - latch characteristics
27:42
lecture10 - Low pass transmission channel - Intersymbol interference, error rate
32:13
lecture11 - First order channel model, ISI(Inter Symbol Interference)
30:53
lecture12 - Channel characteristics-Intersymbol interference, Crosstalk
28:15
lecture13 - Equalizer design
31:56
lecture14 - Equalizer design - minimizing the residual error
33:59
lecture15 - Equalization - Effect on noise and crosstalk
26:36
lecture16 - Tradeoffs between equalization at Transmitter and Receiver
30:59
lecture17 - Design of Transmit equalizers using flip-flops and transconductors
37:04
lecture18 - Transmitter equalizer - design considerations
37:42
lecture19 - Transmitter equalizer - design considerations, realizing variable coefficients
30:31
lecture20 - Differential pair - effect of tail node capacitance
40:29
lecture21 - Continuous time equalizer realization
42:29
lecture22 - Assignment 2 discussion
31:25
lecture23 - Replica biasing, optimizing transmitter swing - 1
31:34
lecture24 - Replica biasing, optimizing transmitter swing
37:45
lecture25 - Analog layout optimization : Equalization at the receiver
39:34
lecture26 - Equalization at the receiver : Basics of adaptation
33:49
lecture27 - LMS adaptation
35:12
lecture28 - Sign-sign LMS adaptation
41:39
lecture29 - LMS implementation details
38:19
lecture30 - Adaptive equalizer implementation, Sample/Hold based equalizer
41:51
lecture31 - Multiplexed and demultiplexed PRBS sequences,Latch vs. amplifier,
38:37
lecture32 - Decision feedback equalizers - elimination of noise enhancement
35:25
lecture33 - Decision feedback equalizers - bit error rate
35:58
lecture34 - Decision feedback equalizers - implementation issues
53:31
lecture35 - Assignment 3 discussion
50:46
lecture36 - Decision feedback equalizers - implementation issues
38:05
lecture37 - Introduction to clock and data recovery - Frequency multiplication using a PLL
49:11
lecture38 - Type 1 PLL; derivation of the phase model of the PLL;
40:20
lecture39 - Type 1 PLL, derivation of the phase model of the PLL,Tri state phase detector
53:30
lecture40 - Reference feedthrough; Tradeoff between reference feedthrough and lock range
51:52
lecture41 - Stability of feedback loops, Derivation of the type II PLL
53:50
lecture42 - Realization of type II PLLs - charge pump, loop filter
57:01
lecture43 - Reference feedthrough in a type II PLL, Phase detector for random data
1:01:04
lecture44 - Linear phase detector for random data
52:07
lecture45 - Linear phase detector - Transfer functions in a PLL
53:51
lecture46 - PLL review
